1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus and an electronic apparatus having a power control function for improving current supply performance of a power control transistor at the time of operation and reducing leakage current at the time of standby.
2. Description of Related Art
Conventionally, methods for employing an MT-CMOS circuit (Multi Threshold-CMOS circuit) are well known as methods for implementing low power consumption of a semiconductor integrated circuit.
FIG. 1 shows a circuit configuration for an MT-CMOS circuit of the related art. An MT-CMOS circuit of the related art is configured from a CMOS logic circuit, and one or both of a power control PchMOS transistor connected across a pseudo power supply line connected to a power supply terminal of the CMOS logic circuit and a high potential side power supply line (VDD), and a power control NchMOS transistor connected across a further pseudo power supply line connected to a power supply terminal of the CMOS logic circuit and a low potential power supply line (VSS).
Further, at the CMOS logic circuit, absolute values of threshold voltages for a PchMOS transistor and an NchMOS transistor for carrying out high-speed operation is set to be small. However, the low threshold voltage MOS transistor has a problem that a large leakage current occurs in a standby state. As a result, a method is disclosed (see, Document 1: Japanese Patent Application Laid-Open No. HEI 6-29834 and Document 2: Japanese Patent Application Laid-Open No. HEI 5-210976) where the absolute values of the threshold voltages of a power control PchMOS transistor and a power control NchMOS transistor are set to be high so that leakage current at the time of standby can be reduced.
Further, to lower on resistance of the power control PchMOS transistor or the power control NchMOS transistor shown in FIG. 1, as shown in FIG. 2, a method is disclosed where a gate voltage lower than VSS is applied to a high threshold voltage PchMOS transistor. Similarly, it is also possible to lower on resistance by applying a gate voltage higher than VDD to a high threshold voltage NchMOS transistor (see, Document 3: Japanese Patent Application Laid-Open No. HEI 8-321763 and Document 4: Japanese Patent Application Laid-Open No. HEI 10-270993).
Moreover, as shown in FIG. 3, rather than using a high threshold voltage PchMOS transistor, it is also possible to use a power control PchMOS transistor with the same threshold voltage as the internal logic circuit, namely use a power control PchMOS transistor having a low threshold voltage. Namely, a method is disclosed where leakage current is reduced by applying a positive voltage across a gate and source. (see the above Document 3 and Document 4).
In FIG. 4, in addition to FIG. 3, on resistance is made further smaller by applying a voltage lower than VSS to the gate (see Document 3).
Further, recently, as shown in FIG. 5, technology is disclosed where it is ensured that excessive voltages are not applied across the gate and drain of the power control MOS transistor (see the above Document 4).
However, with conventional semiconductor integrated circuit apparatus, there are following problems.
With the apparatus disclosed in the above Document 1 and Document 2, a high threshold voltage power control MOS transistor so that it is difficult to set on resistance of a power control MOS transistor to be low. For example, when channel width of a MOS transistor is made large, the on resistance falls, but transistor size becomes large, and chip size of the integrated circuit also becomes large.
It has been proposed to lower on resistance using a method of applying a voltage exceeding the power supply voltage across the gate and source as shown in FIG. 2, using a method of employing a power control MOS transistor having the same threshold voltage as the internal circuit as shown in FIG. 3, or by combinations of these methods. However, it is extremely desirable for on resistance of a power control MOS transistor to be lowered in accompaniment with integrated circuit scale increasing more and more.
Further, with a circuit suppressing the voltage applied across the gate and drain shown in FIG. 5, two power control MOS transistors are connected in series, which results in a problem that the on resistance is two times that of the case of one power control MOS transistor.
Namely, how to keep low leakage current at the time of cut-off of a power control MOS transistor and lower on resistance is lowered is a substantial problem.